A Serializer and Deserializer (SerDes) is an important building block in high speed computer networks and data communications systems. In applications that use a SerDes, no clock is included in the transmission of data signals. Instead, a receiver must extract the timing information from a received data signal and establish a data clock which is used to re-time the received data. The function of extracting the timing information is fulfilled by a clock data recovery (CDR) circuit.
Duty cycle distortion (DCD) is a dominant component of data dependent jitter (DDJ) for serializer and deserializer (SerDes) devices. Jitter is an unwanted variation of one or more signal characteristics in electronics and telecommunications. Jitter may be seen in characteristics such as the interval between successive pulses which results in a receiving CDR failing to accurately reproduce the timing information of a received signal. DDJ is a type of jitter whose effect is data pattern dependent.
DCD is one of the few jitter components that can be controlled to improve SerDes performance. The ability to accurately control DCD enables circuit designers to make better use of limited resources (area, power, simulation time, to name a few) to accomplish design objectives.
Previous attempts to control DCD have been limited to monitoring the DCD of a SerDes circuit, and perform phase adjustment on transmitted signals to reduce or eliminate any DCD present. Additionally, previous attempts have merely considered the DCD experienced in controlled testing environments rather than in multiple environments where temperature, voltage and process may vary to a great degree. Thus, the results of the previous attempts to control DCD are difficult to quantify in a real world environment and are of limited usage to an end user of the SerDes circuit.
What is needed is a way to model DCD over a wide range of control variables and calibrate a SerDes circuit accordingly such that the SerDes circuits efficiency is maximized.